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| PRELIMINARY MX98715BEC APPLICATION NOTE 1. INTRODUCTION The purpose of this application note is to describe the implementation of a PCI bus master 100 Base-TX Fast Ethernet node using MXIC' highly integrated single chip Fast Ethernet NIC controller MX98715BEC. In details, this document presents product overview, programming guide, hardware design and layout recommendations that can help you to quickly and smoothly implement a Fast Ethernet adapter card. As you can find in the MX98715BEC driver diskette, MXIC already provideds a complete set of high quality drivers for easier and more efficient way to interface with MX98715BEC on the most popular Network Operating Systems. Nevertheless, there are still some special applications or environment not covered in the MX98715BEC driver diskette. Driver developers, however, could still refer to the section of driver programming guide to accomplish the required driver. It is recommended that you should be familiar with the MX98715BEC data sheet before reading this guide. The MX98715BEC highly integrates with direct PCI bus interface, including PCI bus master with DMA channel capability, direct EEPROM as well as Boot ROM interface, and large on chip transmit/receive FIFOs. Also, the MX98715BEC is equipped with intelligent IEEE802.3u-compliant Nway auto-negotiation capability allowing a single RJ-45 connector to link with the other IEEE802.3u-compliant device without re-configuration. To optimize operating bandwidth, network data integrity and throughput, the proprietary Adaptive Network Throughput Control (ANTC) function is implemented. For detailed product specification information, please refer to the MX98715BEC data sheet. 3. HARDWARE DESIGN CONSIDERATIONS 3.1 SYSTEM APPLICATION BLOCK DIAGRAM A system block diagram for the MX98715BEC based Fast Ethernet adapter card is shown as following: 2. PRODUCT OVERVIEW The MX98715BEC implements the 10/100Mbps MAC layer and Physical layer on a single chip in accordance with the IEEE 802.3 standard. PCI Bus Boot ROM Osc or Crystal 25MHz MX98715BEC LED EEPROM Magnetic RJ45 Fig. 1 P/N:PM0706 REV. 0.2, NOV. 30, 2000 1 MX98715BEC 3.2 PCI CONNECTION The MX98715BEC provides direct PCI bus interface to PCI connector. Board designers should especially take care of the four pins of TDI,TDO,PRSNT1# & PRSNT2# that are only related to PCI bus connector. Boards that do not implement JTAG Boundary Scan should tight TDI and TDO together to prevent the scan chain from being broken. Both pins PRSNT1# and PRSNT2# should be connected to ground indicating that the board physically exists in a PCI slot and provids information about the total power requirements ( less than 7.5W ) of the board. 3.3 OSCILLATOR OR CRYSTAL The MX98715BEC is designed to operate with a 25MHz oscillator or crystal module. The clock specification of this oscillator should meet 25MHz +/- 50PPM. 3.4 BOOT ROM The MX98715BEC support a direct boot ROM interface allowing diskless workstations to remotely download operating system from network server. For proper operation, the access time of adapt EPROM should not exceed 240ns. 3.5 SERIAL EEPROM The MX98715BEC provides pins EECS,BPA0 (EECK), BPA1 (EEDI) and BPD0 (EEDO) for directly accessing the serial EEPROM. BPA0-1 and BPD0 serve as SK (EECK), DI (EEDI) and DO (EEDO) respectively. The contents of the EEPROM includes the ID information of the MX98715BEC (VendorID, DeviceID, Sub-vendorID, Sub-deviceID and MAC ID), and the configuration parameters for software driver. The EEPROM contents should be programmed according to MXIC's definition as mentioned in Appendix A. Detailed software programming example is described in section 4.5. 3.6 PROGRAMMABLE LED SUPPORT The MX98715BEC provides five pins LED[0:4] to control display LEDs. Displayed messages are programmable through setting CSR9 bits[31:28] & bit24. The maximum sinking current of these output pins is 16mA. Current limiting resistor (560 ohm) should be added to ensure proper operation. The following indicates the configuration setting table for LED display programming. CSR 9<24> LED 4 0 Colision 1 PMEB CSR 9 <28> LED 0 CSR 9<29> LED 1 CSR 9<30> LED 2 CSR 9<31> LED 3 0 Activity 0 Good Link 0 Link Speed 0 Receive 1 Link speed 1 Link Activity 1 Colision 1 F/H duplex 3.7 NETWORK INTERFACE TO MAGNETIC COMPONENT For isolating and impedance matching purpose, an isolating transformer with 1:1 transmit and 1:1 receive turns ratio is required for transmit and receive twisted pair interface. In Appendix B, several transformers that we had verified successfully with MX98715BEC are listed for quick reference purpose. 3.8 OPTIMIZED EQUALIZER COMPONENTS MXIC' Fast Ethernet solution utilizes adaptive equalizer to compensate the attenuation and phase distortion induced by different lengths of cable. To optimize transmit and receive signal quality, pins RTX should be connected to external resistors 1K ohm (1%) and then to ground respectively. 3.9 Remote-Power-On and ACPI application MX98715BEC fully supports Remote-Power-ON and ACPI spec that meet PC99 requirement for powersensitive applications. It accepts the following wake-up events in the power-down mode. * Reception of a Magic Packet. * Reception of a Network wake-up frame. * Detection of change in the network link state. To put MX98715BEC into the sleep mode and enable the wake-up events detection are done as following: P/N:PM0706 REV. 0.2, NOV. 30, 2000 2 MX98715BEC (struct TX_RESOURCE *)((((unsigned int)tx_temp[i])+4)& 1. Write 1 to PPMCSR [8] to enable power management feature. 2. Write the value to PPMCSR [1:0] to determine which power state to enter. If D1, D2 or D3hot state is set, the PC is still turned on and is commonly called entering the Remote Wake-up mode. Otherwise if the main power on a PC is totally shut off, we call that it is in the D3cold state or Remote Power-On mode. To sustain the operation of the Lancard, a 5V standby power is required. Once the PC is turned on, MX98715BEC loads the magic ID from EEPROM and sets it up automatically. No register is needed to be programmed. After then, simply turn off PC to enter D3cold state. In either Remote Wake-up mode or Remote PowerOn mode, the transceiver and the RX block are still alive to monitor the network activity. If one of the three wakeup events occured, the following status is changed: 1. PPMCSR [15] (PME status) is set to 1. 2. CRS5 [28] (WKUPI) is set to 1. 3. PCI interrupt pin INTA# is asserted low. 4. LANWAKE pin is asserted high. 0xfffc); } for (i=0; i This chapter will provide you the necessary information for programming driver for the MX98715BEC based node. Initialization module is introduced first that describes how MX98715BEC is initialized before any other operations can commence, then followed by actual implementation examples for both transmit and receive operations. 4.1 INITIALIZATION initializeTheTransmitRing() { unsigned int i,j; unsigned long physicaladdress; for (i=0; i P/N:PM0706 REV. 0.2, NOV. 30, 2000 3 MX98715BEC rx_resource[i]->buff_2_addr=physicaladdress; } } initialize() { unsigned long physicaladdress; NIC_read_reg(&csr6); NIC_write_reg(&csr6,csr6.value&(~(CSR6_SR|CSR6_ST))); delay(200) : //wait TX&RX to enter stop state, or you can //check bit17~bit19 (RX state) & bit 20~bit21 (TX state) in //CSR5 to assure this condition. InitializeTheTransmitRing (6); InitializeTheReceiveRing (6); NIC_write_reg(&csr0,CSR0_L_SWR); delay(50); NIC_write_reg(&csr0,csr0shadow); //CSR0 shadow=0xFE58A000 get_ea((void far *)rx_resource[0],&physicaladdress); NIC_write_reg(&csr3,physicaladdress); get_ea((void far *)tx_resource[0],&physicaladdress); NIC_write_reg(&csr4,physicaladdress); NIC_write_reg(&csr7,csr7shadow); //csr7shadow=9xE7FFa06D NIC_write_reg(&csr16,csr16shadow); //csr16shadow=0x0B2C000 //Clear status register NIC_write_reg(&csr5,(unsigned long)0xffffffff); NIC_write_reg(&csr6,csr6shadow); //csr6shadow=0x01A8E202 setup_frame(TDES1_SETUP_LAST,perfect); //Initialize CAM to accept self-address/broadcost address //fromes } NIC_write_reg(&csr0,csr0.value|0x020000); tx_pointer=tx_resource[0]; j=0; editmode=1; //TAP=01 while (editmode) { if ((tx_pointer->ownership & 0x80)==0) { j++; j%=tx_pkt_num; if (tx_pointer->command & TDES1_LS_BIT) tx_error_detect(tx_pointer->tstatus); tx_pointer->ownership |= 0x80; tx_pointer=tx_resource[j]; } if (kbhit()) { keycode_get(); if (M_code!=0) { switch (M_code) { case 0x1b: // ESC: quit editmode=0; break; case 0x20: NIC_read_reg(&csr6); NIC_write_reg(&csr6,csr6.value^CSR6_ST); break default: break; } } } } } 4.3 RECEPTION MODULE bmrx() { unsigned char editmode,i,j; unsigned long physicaladdress; struct RX_RESOURCE *rcv_pointer; initialize(); rcv_pointer=rx_resource[0]; j=0; editmode=1; while (editmode) { // if data received 4.2 TRANSMISSION MODULE bmtx() { unsigned char editmode, j; struct TX_RESOURCE *tx_pointer; initialize(); fill_pattern(6); //fill pattern NIC_write_reg(&csr6,csr6.value&(~CSR6_ST)); //stop NIC_read_reg(&csr6); NIC_write_reg(&csr6,csr6.value|CSR6_SF); //store and forward NIC_read_reg(&csr0) P/N:PM0706 REV. 0.2, NOV. 30, 2000 4 MX98715BEC if ((rcv_pointer->frame_length & 0x8000)==0) { j++; j%=6; if (rcv_pointer->rstatus & RDES0_LS) rx_error_detect(rcv_pointer->rstatus); rcv_pointer->frame_length |= 0x8000; rcv_pointer=rx_resource[j]; } if (kbhit()) { keycode_get(); if (M_code!=0) { switch (M_code) { case 0x1b: // ESC: quit editmode=0; break; default: break; } } } } } 4.5 EEPROM ACCESSING The following is a reference code for accessing the contents of EEPROM that stores ID information and node configuration for the MX98715BEC. /************************************* * Read all content from EEPROM **************************************/ eeprom_read() { unsigned int i, address, eeval; char bit; for (address=0; address<64; address++){ NIC_write_reg(&csr9,(unsigned long)0x04800); eeprom_serial_in(0); eeprom_serial_in(1); //command eeprom_serial_in(1); eeprom_serial_in(0); for(i=0; i<6; i++){ //address serial in bit = ((address>>(5-i)) & 0x01) ? 1:0; eeprom_serial_in(bit); } eeval=0; for(i=0; i<16; i++){ //dat serial out NIC_write_reg(&csr9,(unsigned long)0x04803); NIC_read_reg(&csr9); eeval += (((unsigned long)0x008 & csr9.value)>>3)<<(15i); NIC_write_reg(&csr9,(unsigned long)0x04801); } NIC_write_reg(&csr9,(unsigned long)0x04800); c46[address*2] = eeval & 0x0ff; c46[address*2+1] = (eeval >>8) & 0x0ff; } } /************************************* * Write a word to EEPROM **************************************/ eeprom_write(unsigned int address, unsigned int data) { unsigned int i; char bit; eeprom_wen(); NIC_write_reg(&csr9,(unsigned long)0x04800); eeprom_serial_in(0); eeprom_serial_in(1); //command eeprom_serial_in(0); eeprom_serial_in(1); 4.4 SPECIAL CODING of MX98715BEC 4.4.1 SPEED SELECTION Speed selection for MX98715BEC is controlled by internal Nway registers. The Internal NWay registers are removed and protocol selection is controlled by Operation Mode Register (CSR6) and 10Base-T Control Register (CSR14) NWay Active 100F CSR6_PS CSR6_PCS CSR6_FD 0 X 1 1 1 1 0 100H 1 1 0 0 10F 0 X 1 0 10H 0 X 0 0 CSR14_ANE 1 4.4.2 REGISTERS SETTING FOR DEVELOPING YOUR OWN DRIVER The contents of CSR16 for MXIC 10/100Base NIC controllers should be set differently as follow: MX98715BEC = 0x0b2cXXXX Meanwhile, you could directly access the Nway autonegotiation status from CSR20. Detailed format information please refer to MX98715BEC data sheet. P/N:PM0706 REV. 0.2, NOV. 30, 2000 5 MX98715BEC for(i=0; i<6; i++){ //address serial in bit = ((address>>(5-i)) & 0x01) ? 1:0; eeprom_serial_in(bit); } for(i=0; i<16; i++){ //data serial in bit = ((data>>(15-i)) & 0x01) ? 1:0; eeprom_serial_in(bit); } NIC_write_reg(&csr9,(unsigned long)0x04800); NIC_write_reg(&csr9,(unsigned long)0x04801); i=0; do{ i++; NIC_read_reg(&csr9); } while ((!(csr9.value & 0x08)) && (i<10000)); NIC_write_reg(&csr9,(unsigned long)0x04800); if (i==10000) prstring ("Writing EEPROM error !!"); eeprom_wds(); } eeprom_wen() { NIC_write_reg(&csr9,(unsigned long)0x04800); eeprom_serial_in(0); eeprom_serial_in(1); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(1); eeprom_serial_in(1); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); NIC_write_reg(&csr9,(unsigned long)0x04800); } eeprom_wds() { NIC_write_reg(&csr9,(unsigned long)0x04800); eeprom_serial_in(0); eeprom_serial_in(1); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); eeprom_serial_in(0); NIC_write_reg(&csr9,(unsigned long)0x04800); } /************************************* * Serial inject a bit to EEPROM **************************************/ eeprom_serial_in(unsigned int bit2) { NIC_write_reg(&csr9,(unsigned long)0x04800+4*bit2); NIC_write_reg(&csr9,(unsigned long)0x04803+4*bit2); NIC_write_reg(&csr9,(unsigned long)0x04801+4*bit2); } 4.6 AUTO-COMPENSATION ON TRANSCEIVER The driver must set bits CSR20<9> and CSR20<14> high to enable auto-compensation function. Be careful not to clear these two bits while accessing CRS20 at any time. P/N:PM0706 REV. 0.2, NOV. 30, 2000 6 MX98715BEC 5. PCB layout recommendation Introduction: Due to the high frequency and the increasing degree of integration, system board designs are becoming complex. The purpose of this section is to give system designer more information. Such as power stability, placement, signal trace routing and de-coupling capacitor. 5.1 Power / Ground consideration It is recommended to separate power plane into 3 domains (Power for digital , analog and receive section). Segmented power supplies reduces noise from one section to another. It is also recommended to separate ground plane into 3 domains ( Digital Ground, Analog Ground and Receive Ground). The reason for separating is to prevent digital noise from coupling onto the analog or receive ground. All power/ground lines should be as wide as possible to allow noise de-coupling and efficient low resistive paths for supply current. 3.3V bead V digital GND GNDR V analog 40mil Bridge V receive GND GNDA Depending upon the environment, any or all of these filters may be simplified.o GNDR (Receive ground) PCI Interface GNDA (Analog ground) GND (digital ground) P/N:PM0706 REV. 0.2, NOV. 30, 2000 7 MX98715BEC 5.2 Board Layout / Trace Routing 90 degree corners should be avoided, smooth cornering is preferred. Keep the lengths of clock lines short and minimize the numbers of VIAs. All pair lines ( i.e. TX+/- , RX+/-) are of the equal length and run in parallel then possible noise is common and can be ignored on different inputs. Magnetic Magnetic Tx+ Tx- Tx+ Tx- A good practice is that never run transmit and receive pair too close. Crosstalk may become a problem. Magnetic Magnetic Tx+ TxRx+ Rx- Tx+ TxRx+ Rx- The ground shield of clock line may reduce extra noise. Tx+ TxRx+ Rx- Ground Shield Oscillator P/N:PM0706 REV. 0.2, NOV. 30, 2000 8 MX98715BEC All differential pair ( Tx +/ - , Rx +/-) to the magnetic should have matched impedance. See schematics for details. V 50 Tx+ TxV Magnetic 50 Rx+ Rx- 100 Ohm A chassis ground is used to isolate the cable side and ground. System Ground Chassis Ground Magnetic 5.3 Component placement General: External components are placed as close as possible Osc/Crystal IC Eeprom Magnetic RJ-45 BootRom P/N:PM0706 REV. 0.2, NOV. 30, 2000 9 MX98715BEC De-coupling capacitor De-coupling cap should be placed close to power pin. It stabilize current to the device and de-coupling noise from the power plane to ground. PIN 0.1 U IC Analog Region 82. VDD 85. VDD 94. VDD 97. VDD 103. VDD 105. VDD Receive Region 88. GND 89. VDD 90. GND 91. VDD Digital Region Others 83. GND 84. GND 95. GND 96. GND 100. GND 101. GND 104. GND 106. GND Transformer RXRX+ TXTX+ Receive Region Bead OSC or crystal 25MHz 94 93 88 85 82 80 Analog Region Bead 106 111 Digital Region MX98715BEC 128 1 Fig. 2 P/N:PM0706 REV. 0.2, NOV. 30, 2000 10 MX98715BEC APPENDIX A: EEPROM FORMAT BYTE OFFSET (HEX) 00-13 14 15 16 17 18 19 1a 1b 1c 1d 1e-39 3a 3b 3c-59 5a 5b 5c 5d 5e-65 66 67 DESCRIPTIONS Reserved MAC ID Byte0 ( is automatically loaded into IC ) MAC ID Byte1 ( is automatically loaded into IC ) MAC ID byte2 ( is automatically loaded into IC ) MAC ID byte3 ( is automatically loaded into IC ) MAC ID byte4 ( is automatically loaded into IC ) MAC ID byte5 ( is automatically loaded into IC ) Magic Packet ID Byte0 ( is automatically loaded into IC ) Magic Packet ID Byte1 ( is automatically loaded into IC ) Magic Packet ID Byte2 ( is automatically loaded into IC ) Magic Packet ID Byte3 ( is automatically loaded into IC ) Reserved Magic Packet ID Byte4 ( is automatically loaded into IC ) Magic Packet ID Byte5 ( is automatically loaded into IC ) Reserved LSB of Sub-Device ID ( is automatically loaded into IC ) MSB of Sub-Device ID ( is automatically loaded into IC ) LSB of Sub-Vendor ID ( is automatically loaded into IC ) MSB of Sub-Vendor ID ( is automatically loaded into IC ) Reserved bit0 : must be 0, modem interface disable bit0 : CRUNEN : Control the functionality of CLKRUNB pin 0 : MX98715BEC always refuses to slow or stop the clock 1 : MX98715BEC will agree to slow or stop the clock bit1 : Trdysel : IBM bridge bug fix bit4 : HWDISWOL : Disable the wake-on-Lan feature bit7 : MISHW7 : Select the power of PMD while system power up. 1 : power on the PMD. 0 : power down the PMD. MLDTHRE1 [5 : 0] bit0~bit5 loaded into CSR33 [11 : 6] MLDTHRE3 [5 : 0] bit0~bit5 loaded into CSR33 [23 : 18] MLDTHRE2 [5 : 0] bit0~bit5 loaded into CSR33 [17 : 12] MLDTHRE2 [5 : 0] bit0~bit5 loaded into CSR34 [23 : 18] 68 6A 6B 6C P/N:PM0706 REV. 0.2, NOV. 30, 2000 11 MX98715BEC 6D 6E 6F 70 MGCTHRE1 [5 : 0] bit0~bit5 loaded into CSR34 [17 : 12] MVCRTHRE2 [5 : 0] bit0~bit5 loaded into CSR34 [11 : 6] MVCPTHRE1 [5 : 0] bit0~bit5 loaded into CSR34 [5 : 0] Network ID index: to indicates the starting address of Network ID in length of continuous 6 bytes. The content of this field could be in the range of 00-04h, or 10-14h, or 2124h, or 31-34h. IC always automatically load ID from 14h after reset or power up. Reserved, and should be set to 0 LED option: The conent of this field is automatically loaded into CSR9 register for LED option. 71-75 76 77 78-79 7a 7b 7c 7d 7e-7f Bit0:CSR9<28>=LED0SEL Bit1:CSR9<29>=LED1SEL Bit2:CSR9<30>=LEDSEL2 Bit3:CSR9<31>=LEDSEL3 Bit4:CSR9<24>=LEDSEL4 Bit5:CSR9<25>:WKFCAT0 Bit6:CSR9<26>:WKFCAT1 Bit7:Must be zero LED programing option table 0 1 LED0SEL ACT SPEED LED1SEL LINK LINK/ACT LED2SEL SPEED COL LED3SEL RX FULL/HALF LED4SEL COL PMEB Miscellaneous options is automatically loaded into CSR21 register & IC. : Bit0:MPHITDIS : set 1 to disable magic packet detection loaded into CSR21.2 Bit1:LNKCHGDIS : Set 1 to disable link packet detection loaded into CSR21.3 Bit2:Retry bug fix. Bit3:WKFCATEN, wake up frame catenation enable. Reserved, and should be set to 0 LSB of Device ID MSB of Device ID LSB of Vendor ID MSB of Vendor ID Reserved, and should be set to 0 P/N:PM0706 REV. 0.2, NOV. 30, 2000 12 MX98715BEC APPENDIX B: SPECIAL COMPONENTS 1.MAGNETIC A.BASIC ELECTRICAL SPECIFICATION Turn Ratio OCL LL Cww DCR Isolation Resistance Isolation Voltage Rise/Fall Time Insertion Loss (100 KHz to 100 MHz) CMDR & DCMR (100 KHz to 80 MHz) Cross Talk (100KHz to 80 MHz) B. Transformer REFERENCE VENDORS Vendor Valor PE BelFuse Delta Taimic Transmit 1:1 Receive 1:1 350uH min measured between 0 and 70 with a 0.1V rms, 100KHz C signal at a DC. bias between 0 and 8mA. 0.4uH Max at >1MHz 18pF Max 0.9W Max per winding not less than 1GW @ 2000V rms 2000V rms Min @ 60Hz for 1 min 3ns Min 4ns Max -1.1 dB Max 38 dB Min -38 dB Max Part No ST6118 (PT4171S) PE68515 S558-5999-15 LF8200 HSIP-002 2.CRYSTAL A. BASIC ELECTRICAL SPECIFICATION CL=((C1*C2)/(C1+C2))+CIC+ C, Rd 100 ohm, R 1M ohm CL=Crystal's external load capacitor Specified by crystal's specification CIC=MX98715BEC internal capacitor, C=PCB's stray capacitance Assume C1=C2=CExt, CL=1/2CExt + 7pf + 3pf if CL=20pf, than CExt=C1=C2=20pf. P/N:PM0706 IC 7pF R Rd C=3pf, C1 C2 REV. 0.2, NOV. 30, 2000 13 MX98715BEC B. CRYSTAL REFERENCE VENDORS SPK 25MHz50PPM NDK JEN JAAN ENTERPRISE 3. SPECIAL REQUIREMENT ON RESISTORS & BEAD Resistors for RTX=1K ohm 1% Ferrite Bead maximum current capacity for analog Vdd > 300mA Ferrite Bead maximum current capacity for Receive Region Vdd > 100mA P/N:PM0706 REV. 0.2, NOV. 30, 2000 14 MX98715BEC REVISION HISTORY REVISION 0.0 0.1 0.2 DESCRIPTION modify PCB recommendation modify analog region receive region & fig.2 modify special requirement on resistors & bead PAGE P7 P10 P14 DATE MAR/27/2000 JUL/11/2000 NOV/30/2000 P/N:PM0706 REV. 0.2, NOV. 30, 2000 15 MX98715BEC TOP SIDE MARKING MX98715BEC line 1 : MX98715B is MXIC parts No. "E" : PQFP "C" : commercial grade line 2 : Assembly Date Code. line 3 : Wafer Lot No. line 4 : State C9930 TA777001 TAIWAN MACRONIX INTERNATIONAL CO., LTD. HEADQUARTERS: TEL:+886-3-578-6688 FAX:+886-3-578-2888 EUROPE OFFICE: TEL:+32-2-456-8020 FAX:+32-2-456-8021 JAPAN OFFICE: TEL:+81-44-246-9100 FAX:+81-44-246-9105 SINGAPORE OFFICE: TEL:+65-347-8385 FAX:+65-348-8096 TAIPEI OFFICE: TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 16 |
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